Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film

ABSTRACT

A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film and a silicon nitride film being formed, p-type impurity ions are implanted in a Y direction from diagonally above. As for an implant angle α of the ion implantation, an implant angle is adopted that satisfies the relationship tan −1  (W2/T)&lt;α≦tan −1  (W1/T), where W1 is an interval between a first portion and a fourth portion and an interval between a third portion and a sixth portion; W2 is an interval between a second portion and a fifth portion; T is a total film thickness of the silicon oxide film and the silicon nitride film. When the implant angle α is controlled within that range, impurity ions are implanted into a second side surface and a fifth side surface through a silicon oxide film.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.11/767,734, filed Jun. 25, 2007, which is a divisional of U.S.application Ser. No. 11/292,360 filed Dec. 2, 2005, which is adivisional of U.S. application Ser. No. 10/730,099, filed Dec. 9, 2003,now U.S. Pat. No. 6,998,319 each of which is hereby incorporated byreference. This application is based upon and claims the benefit ofpriority from the prior Japanese patent application No. 2003-143438filed May 21, 2003.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to methods of manufacturing semiconductordevices, and more particularly to a method of manufacturing asemiconductor device having a DRAM capacitor.

2. Description of the Background Art

A conventional method of manufacturing a semiconductor device having aDRAM capacitor has the following steps, which are carried out in thefollowing order: (a) partially forming an element isolating insulationfilm in an upper surface of a silicon substrate, (b) ion-implanting animpurity in a direction perpendicular to the upper surface of thesilicon substrate to form a doped channel region, a channel cut region,and a well region, all of which are of p-type, within the siliconsubstrate that is in an element forming region, (c) forming a gateinsulating film on the upper surface of the silicon substrate that iswithin the element forming region using a thermal oxidation technique,(d) forming a gate electrode on the gate insulating film, (e) forming asource region and a drain region, both of which are of n-type, in theupper surface of the silicon substrate, the source region and drainregion forming a pair such as to sandwich a channel forming region belowthe gate electrode, (f) forming a first interlayer dielectric filmentirely, (g) forming a first contact plug connected to the drain regionin the first interlayer dielectric film, (h) forming a bit lineconnected to the first contact plug, (i) forming a second interlayerdielectric film entirely, (j) forming a second contact plug connected tothe source region in the first and second interlayer dielectric films,(k) forming a third interlayer dielectric film entirely, (j) forming acapacitor lower electrode connected to the second contact plug in thethird interlayer dielectric film, (m) forming a capacitor dielectricfilm on the capacitor lower electrode, and (n) forming a capacitor upperelectrode on the capacitor dielectric film.

Japanese Patent Application Laid-Open Nos. 10-65153, 9-237829, and8-250583, for example, disclose methods of manufacturing a semiconductordevice including the step of forming a doped channel region in a siliconsubstrate.

According to the conventional methods of manufacturing a semiconductordevice, however, the gate insulating film is formed after the dopedchannel region is formed. For this reason, part of the impuritycontained in the doped channel region is absorbed into the gateinsulating film by the heat treatment for forming the gate insulatingfilm. As a result, the impurity concentration of the doped channelregion becomes lower than a desired value, thereby reducing thethreshold voltage of a memory cell transistor. This tendency isparticularly noticeable in a boundary portion between the elementisolating insulation film and the doped channel region, and aconsiderable reduction in the threshold voltage of memory celltransistors occurs when the width of the doped channel region becomesnarrower than a certain value (the phenomenon known as “inverse narrowwidth effect”).

It is possible to compensate the reduction in the impurity concentrationby ion-implanting a p-type impurity at a higher concentration than adesired value when forming doped channel regions. However, since thehigh-concentration p-type impurity is implanted into the regions inwhich n-type source and drain regions are to be formed, the followingproblems arise.

Because the impurity concentration in the source and drain regionsreduces, the contact resistance between the source region and the secondcontact plug increases. As a consequence, the performance of memory celltransistors degrades, leading to the problem of deteriorating data writecharacteristics.

In addition, electric field strength becomes high in the boundaryportion between the source region and the channel forming region and inthe boundary portion between the source region and the element isolatinginsulation film. As a result, junction leakage current increases,leading to the problem of deteriorating device characteristics (forexample, refresh characteristics) of DRAMs.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a methodof manufacturing a semiconductor device that is capable of suppressingreduction in a impurity concentration in a doped channel region, whichis caused by formation of a gate insulating film, without deterioratingwrite characteristics and refresh characteristics.

According to a first aspect of the present invention, a method ofmanufacturing a semiconductor device includes the following steps (a)through (k). The step (a) is to form a first substantially H-shaped maskmaterial and a second substantially H-shaped mask material on a mainsurface of a semiconductor substrate, the first mask material having afirst portion, a second portion, and a third portion connected in thatorder along a first direction in plan view and wherein a dimension ofthe second portion with respect to a second direction in plan view thatis perpendicular to the first direction is smaller than dimensions ofthe first and third portions with respect to the second direction, thesecond mask material having a fourth portion, a fifth portion, and asixth portion connected in that order along the first direction andwherein a dimension of the fifth portion with respect to the seconddirection is smaller than dimensions of the fourth and sixth portionswith respect to the second direction, so that the first and fourthportions, the second and fifth portions, and the third and sixthportions are each mutually spaced apart and aligned along the seconddirection. The step (b) is to etch the semiconductor substrate using thefirst and second mask materials as etch masks, to form in the mainsurface a recessed portion having a first side surface, a second sidesurface, and a third side surface that are defined by the semiconductorsubstrate below the first to third portions, and a fourth side surface,a fifth side surface, and a sixth side surface that are defined by thesemiconductor substrate below the fourth to sixth portions. The step (c)is to implant impurity ions in the second direction from diagonallyabove, with the first and second mask materials being formed on the mainsurface, to form first doped channel regions of a first conductive typeonly in the second and fifth side surfaces among the first to sixth sidesurfaces. The step (d) is performed after the step (c). The step (d) isto form an element isolating insulation film by filling the recessedportion to define respective portions of the semiconductor substratewhere the first and second mask materials are formed in the step (a) asa first element forming region and a second element forming region. Thestep (e) is to form second doped channel regions of the first conductivetype respectively within the main surface that is in the first andsecond element forming regions. The step (f) is performed after the step(c). The step (f) is to remove the first and second mask materials. Thestep (g) is performed after the step (f). The step (g) is to form aninsulating film on the main surface that is in the first and secondelement forming regions. The step (h) is to form a conductive film on astructure obtained by the step (g). The step (i) is to pattern theconductive film to form a gate electrode above the main surface on whichthe second and fifth portions are formed in the step (a), the gateelectrode extending along the second direction. The step ( ) is to formfirst source-drain regions of a second conductive type being differentfrom the first conductive type, in the main surface in which the firstand fourth portions are formed in the step (a). The step (k) is to formsecond source-drain regions of the second conductive type in the mainsurface in which the third and sixth portions are formed in the step(a).

It is possible to suppress reduction in the impurity concentration inthe doped channel regions, which arises from formation of the gateinsulating film.

According to a second aspect of the present invention, a method ofmanufacturing a semiconductor device includes the following steps (a)through (k). The step (a) is to form a first mask material, a secondmask material, and a third mask material on a main surface of asemiconductor substrate, the first mask material having a first portion,a second portion, and a third portion connected in that order along afirst direction in plan view, the second mask material having a fourthportion, a fifth portion, and a sixth portion connected in that orderalong the first direction, and the third mask material having a seventhportion, an eighth portion, and a ninth portion connected in that orderalong the first direction, so that the third, fourth and ninth portionsare mutually spaced apart and aligned in that order along a seconddirection in plan view that is perpendicular to the first direction,that the second and eighth portions are mutually spaced apart andaligned along the second direction, and that the second and fifthportions are not aligned along the second direction. The step (b) is toetch the semiconductor substrate using the first to third mask materialsas an etch mask to form in the main surface a recessed portion having afirst side surface, a second side surface, and a third side surface thatare defined by the semiconductor substrate below the first to thirdportions, respectively, a fourth side surface, a fifth side surface, anda sixth side surface that are defined by the semiconductor substratebelow the fourth to sixth portions, respectively, and a seventh sidesurface, an eighth side surface, and a ninth side surface that aredefined by the semiconductor substrate below the seventh to ninthportions. The step (c) is to implant impurity ions in the seconddirection from diagonally above, with the first to third mask materialsbeing formed on the main surface, to form first doped channel regions ofa first conductive type only in the second side surface of the secondand third side surfaces, only in the fifth side surface of the fourthand fifth side surfaces, and only in the eighth side surface of theeighth and ninth side surfaces. The step (d) is performed after the step(c). The step (d) is to form an element isolating insulation film byfilling the recessed portion to define respective portions of thesemiconductor substrate where the first to third mask materials areformed in the step (a) as a first element forming region, a secondelement forming region, and a third element forming region. The step (e)is to form second doped channel regions of the first conductive typewithin the main surface that is in the first to third element formingregions, respectively. The step (f) is performed after the step (c). Thestep (f) is to remove the first to third mask materials. The step (g) isperformed after the step (f). The step (g) is to form an insulating filmon the main surface that is in the first to third element formingregions. The step (h) is to form a conductive film on a structureobtained by the step (g). The step (i) is to pattern the conductive filmto form a gate electrode above the main surface on which the second,fifth, and eighth portions are formed in the step (a), the gateelectrode extending along the second direction. The step (j) is to formfirst source-drain regions of a second conductive type being differentfrom the first conductive type, in the main surface in which the first,sixth, and seventh portions are formed in the step (a). The step (k) isto form second source-drain regions of the second conductive type in themain surface in which the third, forth, and ninth portions are formed inthe step (a).

It is possible to suppress reduction in the impurity concentration inthe doped channel regions, which arises from formation of the gateinsulating film.

According to a third aspect of the present invention, a method ofmanufacturing a semiconductor device includes the following steps (a)through (e). The step (a) is to form an insulating film on a mainsurface of a semiconductor substrate. The step (b) is to form aconductive film on the insulating film. The step (c) is to implant ionsof an impurity into the main surface through the conductive film and theinsulating film to form doped channel regions. The step (d) is topattern the conductive film to form a gate electrode. The step (e) is tointroduce an impurity into the main surface that is exposed from thegate electrode to form source-drain regions.

It is possible to suppress reduction in the impurity concentration inthe doped channel regions, which arises from formation of the gateinsulating film.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top plan view showing a structure of a semiconductor deviceaccording to a first preferred embodiment of the present invention;

FIG. 2 is a cross-sectional view showing a cross-sectional structure ofthe semiconductor device shown in FIG. 1;

FIG. 3 is a cross-sectional view showing, in order of manufacturingsteps, a method of manufacturing the semiconductor device according tothe first preferred embodiment of the present invention;

FIG. 4 is a top plan view showing a formation pattern of a siliconnitride film, corresponding to FIG. 1;

FIGS. 5 through 11 are cross-sectional views showing, in order ofmanufacturing steps, the method of manufacturing the semiconductordevice according to the first preferred embodiment of the presentinvention;

FIG. 12 is a top plan view showing a structure of a semiconductor deviceaccording to a second preferred embodiment of the present invention;

FIG. 13 is a cross-sectional view showing a cross-sectional structureconcerning a position along the line XIII-XIII shown in FIG. 12;

FIG. 14 is a top plan view showing a formation pattern of a siliconnitride film, corresponding to a portion of FIG. 12;

FIGS. 15 through 19 are cross-sectional views showing, in order ofmanufacturing steps, a method of manufacturing the semiconductor deviceaccording to the second preferred embodiment of the present invention;

FIGS. 20 and 21 are cross-sectional views showing, in order ofmanufacturing steps, a method of manufacturing a semiconductor deviceaccording to a third preferred embodiment of the present invention;

FIGS. 22 and 23 are cross-sectional views showing, in order ofmanufacturing steps, a method of manufacturing a semiconductor deviceaccording to a fourth preferred embodiment of the present invention;

FIG. 24 is a top plan view showing a structure of a semiconductor deviceaccording to a fifth preferred embodiment of the present invention;

FIG. 25 is a cross-sectional view showing a cross-sectional structureconcerning a position along the line XXV-XXV shown in FIG. 24;

FIGS. 26 and 27 are cross-sectional views showing, in order ofmanufacturing steps, a method of manufacturing the semiconductor deviceaccording to the fifth preferred embodiment of the present invention;

FIGS. 28 through 31 are cross-sectional views showing, in order ofmanufacturing steps, a method of manufacturing a semiconductor deviceaccording to a sixth preferred embodiment of the present invention;

FIGS. 32 through 35 are cross-sectional views showing, in order ofmanufacturing steps, a method of manufacturing a semiconductor deviceaccording to a seventh preferred embodiment of the present invention;and

FIG. 36 is a top plan view showing a structure of a semiconductor deviceaccording to an eighth preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Preferred Embodiment

FIG. 1 is a top plan view showing a structure of a semiconductor deviceaccording to a first preferred embodiment of the present invention.Element forming regions AR1 and AR2 having a substantially H-shapedupper surface structure are defined by an element isolating insulationfilm 4. The element forming regions AR1 and AR2 are spaced apart fromeach other and aligned along a Y direction.

In the element forming region AR1, a first transistor is formed that hasa source region 1S, a drain region 1D, a doped channel region 1C, and agate structure 3. Likewise, in the element forming region AR2, a secondtransistor is formed that has a source region 2S, a drain region 2D, adoped channel region 2C, and the gate structure 3. In the example shownin FIG. 1, the gate structure 3 that the first transistor has and thegate structure 3 that the second transistor has are connected to eachother. The first and second transistors are, for example, memory celltransistors of a DRAM, transistors constituting a peripheral circuitthereof, or transistors constituting a logic circuit thereof. In thefollowing, an example in which the first and second transistors are bothN-channel MOSFETs is described.

The source region 1S, the doped channel region 1C, and the drain region1D are aligned in that order along an X direction. Likewise, the sourceregion 2S, the doped channel region 2C, and the drain region 2D arealigned in that order along the X direction. The source region 1S andthe source region 2S, the doped channel region 1C and the doped channelregion 2C, and the drain region 1D and the drain region 2D, are eachmutually spaced apart and aligned along the Y direction. An interval W1between the doped channel region 1C and the doped channel region 2C iswider than an interval W2 between the source region 1S and the sourceregion 2S and the interval W2 between the drain region 1D and the drainregion 2D.

FIG. 2 depicts cross-sectional views showing a cross-sectional structureof the semiconductor device shown in FIG. 1. In FIG. 2, views (A), (B),and (C) show the cross-sectional structures taken along the linesIIA-IIA, IIB-IIB, and IIC-IIC shown in FIG. 1, respectively.

FIGS. 3 and 5 to 11 are cross-sectional views showing, in order ofmanufacturing steps, a method of manufacturing a semiconductor deviceaccording to the first preferred embodiment. The views (A) to (C) ineach of the figures correspond to the views (A) to (C) of FIG. 2,respectively.

First, referring to FIG. 3, a silicon oxide film and a silicon nitridefilm are formed in that order entirely on an upper surface of an n-typesilicon substrate 10. It should be noted, however, that a siliconoxynitride film may be formed in place of the silicon oxide film.Alternatively, in place of the silicon nitride film, a polysilicon filmor a layered film of a silicon nitride film and a polysilicon film maybe formed. Next, by patterning these films, a silicon oxide film 20 anda silicon nitride film 21 are formed. Subsequently, using the siliconnitride film 21 as an etch mask, the silicon substrate 10 is etched awayby a predetermined film thickness using an anisotropic dry etchingtechnique. This forms a recessed portion 22 in the upper surface of thesilicon substrate 10. Then, using an oxidation furnace or a singlewafer-type lamp oxidation apparatus, a silicon oxide film 13 having afilm thickness of about several nanometers to several tens of nanometersis formed on the side surfaces and the bottom surface of the recessedportion 22 by a thermal oxidation technique at about 900 to 1150° C.This recovers crystal defects in the silicon substrate 10 that areproduced by damages arising from the etching for forming the recessedportion 22.

FIG. 4 is a top plan view showing a formation pattern of the siliconnitride film 21 corresponding to FIG. 1. The silicon nitride film 21that corresponds to the element forming region AR1 (denoted by referencecharacter 21 a in FIG. 4) has a first portion 211, a second portion 212,and a third portion 213, which are connected in that order along the Xdirection. The silicon nitride film 21 a has a substantially H-shapedupper surface structure, and the dimension of the second portion 212with respect to the Y direction is smaller than the dimensions of thefirst portion 211 and the third portion 213 with respect to the Ydirection. Likewise, the silicon nitride film 21 that corresponds to theelement forming region AR2 (denoted by reference character 21 b in FIG.4) has a fourth portion 214, a fifth portion 215, and a sixth portion216, which are connected in that order along the X direction. Thesilicon nitride film 21 b has a substantially H-shaped upper surfacestructure, and the dimension of the fifth portion 215 with respect tothe Y direction is smaller than the dimensions of the fourth portion 214and the sixth portion 216 with respect to the Y direction. The firstportion 211 and the fourth portion 214, the second portion 212 and thefifth portion 215, and the third portion 213 and the sixth portion 216are each mutually spaced apart and aligned along the Y direction. Therecessed portion 22 has first to sixth side surfaces 10A1 to 10A6defined by the silicon substrate 10 below the first to sixth portions211 to 216.

Subsequent to FIG. 3, referring to FIG. 5, ions 231, 232 of a p-typeimpurity such as B, BF2, or In are implanted at a concentration of about1E11/cm2 to 1E14/cm2 in the Y direction from diagonally above, with thesilicon oxide film 20 and the silicon nitride film 21 having beenformed. The ion implantation is sequentially carried out in opposingdirections +Y and −Y, as indicated by arrows Y1 and Y2 in FIG. 1.

As for implant angle α of the ion implantation (that is, an angle formedby an implant direction of the impurity ions 231 and 232 and a directionof the normal to the upper surface of the silicon substrate 10), animplant angle is adopted that falls within a range that satisfies therelationship tan−1(W2/T)<α≦tan−1(W1/T), where W2 represents an intervalbetween the first portion 211 and the fourth portion 214 and an,internal between the third portion 213 and the sixth portion 21 6 shownin FIG. 4, W1 is an interval between the second portion 212 and thefifth portion 215, and T is a total film thickness of the silicon oxidefilm 20 and the silicon nitride film 21.

When the implant angle α is controlled within that range, the impurityions 231 and 232 are implanted through the silicon oxide film 13 in thesecond side surface 10A2 and the fifth side surface 10A 5 shown in FIG.4. As a result, as shown in view (A) of FIG. 5, p-type doped channelregions 51 and 52 are formed within the upper surface of the siliconsubstrate 10 that is in the element forming regions AR1 and AR2,respectively. On the other hand, due to the shadowing effect of thesilicon oxide film 20 and the silicon nitride film 21, the impurity ions231 and 232 are not implanted to the first side surface 10A1, the thirdside surface 10A 3, the fourth side surface 10A4, and the sixth sidesurface 10A6 that are shown in FIG. 4. As a result, as shown in view (B)of FIG. 5, the doped channel regions 51 and 52 are not formed.

Next, referring to FIG. 6, a silicon oxide film 24 having such a filmthickness that it can completely fill up the recessed portion 22 isentirely formed by a coating technique or a CVD technique using highdensity plasma. The silicon oxide film 24 may be doped with impuritysuch as F, P, or B.

Then, referring to FIG. 7, the silicon oxide film 24 is polished by aCMP technique until an upper surface of the silicon nitride film 21 isexposed.

Subsequently, referring to FIG. 8, in order to adjust the height of anupper surface of the element isolating insulation film 4, the siliconoxide film 24 is removed by a desired film thickness using an aqueoussolution of HF or the like. Next, the silicon nitride film 21 is removedusing a hot phosphoric acid solution.

Then, referring to FIG. 9, in order to form a CMOS transistor, animpurity such as B is ion-implanted into the silicon substrate 10through the silicon oxide film 20, thereby forming a p-type well region11. Reference numeral 11 in FIG. 9 represents a location in which theimpurity concentration shows a peak in the well region. Subsequently, inorder to improve isolation breakdown voltage, a p-type channel cutregion 12 is formed by ion-implanting an impurity such as B, BF2, or Ininto the silicon substrate 10 through the silicon oxide film 20. Next,in order to adjust the threshold voltage of the transistors, an impuritysuch as B, BF 2, or In is ion-implanted at a concentration of about1E11/cm 2 to 1E14/cm 2 into the silicon substrate 10 through the siliconoxide film 20. Thus, p-type doped channel regions 11C and 2C are formedin the upper surface of the silicon substrate 10. Thereafter, theimpurities that have been ion-implanted in the silicon substrate 10 areactivated by carrying out a heat treatment at about 800 to 1100° C.using a lamp annealing technique.

Next, referring to FIG. 10, the silicon oxide film 20 is removed usingan aqueous solution of HF or the like. Thus, the upper surface of thesilicon substrate 10 that is in the element forming regions AR1 and AR2is exposed. Also, a portion of the silicon oxide film 24 is removed toform a silicon oxide film 14, thus forming a trench-shaped elementisolating insulation film 4 having the silicon oxide films 13 and 14.Subsequently, using an oxidation furnace at about 700 to 850°, or a lampoxidation apparatus at about 900 to 1100° C., silicon oxide films 15 1and 15 2 functioning as gate insulating films are formed on the uppersurface of the silicon substrate 10 that is in the element formingregions AR1 and AR2. It should be noted that a silicon oxynitride film,or a layered film of a silicon oxide film and a silicon oxynitride filmmay be formed in place of the silicon oxide films 15 1 and 15 2. Then,by a CVD technique or the like, a conductive film 16 is formed on thesilicon oxide films 15 1 and 15 2 and on the element isolatinginsulation film 4. The conductive film 16 is a polysilicon film, a metalfilm (W, Ti, Al, Cu, or the like), a metal silicide film, a metalnitride film, or a layered film thereof. Next, using a CVD technique orthe like, a silicon nitride film 17 is formed on the conductive film 16.It should be noted that a silicon oxide film, or a layered film of asilicon oxide film and a silicon nitride film may be formed in place ofthe silicon nitride film 17.

Next, referring to FIG. 11, the silicon nitride film 17 is patterned bya photolithography technique and an anisotropic dry etching technique.Then, using the silicon nitride film 17 as an etch mask, the conductivefilm 16 is etched by an anisotropic dry etching technique. The portionof the conductive film 16 that has not been etched away functions as agate electrode. Next, using a lamp oxidation technique or a normalthermal oxidation technique, the conductive film 16 is oxidized ornitrided in a mixed gas atmosphere of O2, NO, N2O, NH3, H2, etc., toform an insulating film 18.

Subsequently, using the silicon nitride film 17 as an implant mask, animpurity such as P, As, or Sb is ion-implanted so as to form n-typesource regions 1S and 2S and n-type drain regions 1D, 2D in the uppersurfaces of the silicon substrate 10. With the manufacturing steps thusdescribed, the structure shown in FIG. 2 is obtained.

As described above, in the method of manufacturing the semiconductordevice according to the first preferred embodiment, the silicon oxidefilms 15 1 and 15 2, which function as the gate insulating films, areformed in the step shown in FIG. 10, after the doped channel regions 5 1and 5 2 are formed in the step shown in FIG. 5 and then the dopedchannel regions 1C and 2C are formed in the step shown in FIG. 9.Therefore, even if part of the impurity contained in the doped channelregions 5 1, 5 2, 1C and 2C are absorbed in the gate insulating filmsbecause of the heat treatment for forming the gate insulating films, itis possible to suppress reduction in the impurity concentration in thedoped channel regions in comparison with the conventional manufacturingmethods in which the doped channel regions 5 1 and 5 2 are not formed.As a consequence, reduction in the threshold voltages of the first andsecond transistors can be suppressed.

Moreover, as shown in FIG. 1, the doped channel regions 5 1 and 5 2 areformed under the gate structure 3 and in the boundary portions betweenthe element isolating insulation film 4 and the doped channel regions 1Cand 2C; therefore, the inverse narrow width effect is effectivelyprevented from occurring.

Furthermore, in the step shown in FIG. 5, the p-type impurity ions 23 1,23 2 are implanted in the Y direction from diagonally above, and inaddition, the implant angle .alpha. of the ion implantation iscontrolled within the range tan.sup.−1(W2/T)<α≦tan−1(W1/T); therefore,of the first to sixth side surfaces 10A 1 to 10A 6 shown in FIG. 4, onlyin the second side surface 10A 2 and the fifth side surface 10A 5, thedoped channel regions 5 1 and 5 2 are formed in a self-aligned manner.Consequently, reduction in the impurity concentrations in the n-typesource regions 1S and 2S as well as the drain regions 1D and 2D becauseof the formation of the p-type doped channel regions 5 ₁ and 5 ₂ can beappropriately avoided.

Second Preferred Embodiment

The second preferred embodiment describes an example in which theinvention according to the foregoing first preferred embodiment isapplied to DRAM memory cells.

FIG. 12 depicts a top plan view showing a structure of a semiconductordevice according to a second preferred embodiment of the presentinvention. FIG. 13 depicts a cross-sectional view showing across-sectional structure concerning a position along the line XIII-XIIIshown in FIG. 12. Referring to FIG. 12, a plurality of element formingregions AR (represented by reference characters AR 11, AR 12, AR 21, AR31, and AR 32 in FIG. 12) are defined by the element isolatinginsulation film 4. The element forming region AR 11 and the elementforming region AR 31 both of which belong to a common column in a memorycell array, and the element forming region AR 12 and the element formingregion AR 32, both of which belong to another common column, are eachmutually spaced apart and aligned along the Y direction. The elementforming region AR 11 and the element forming region AR 12, both of whichbelong to a common row, and the element forming region AR 3, and theelement forming region AR 32, both of which belong to a common row, areeach mutually spaced apart and aligned along the X direction. Theelement forming region AR 21 is formed so that it is staggered withrespect to the element forming region AR11 by half of the formationpitch of the element forming regions AR along the X direction. That is,a so-called half pitch cell is constructed.

Referring to FIGS. 12 and 13, in each one of the element forming regionsAR, two memory cell transistors are formed sharing a drain region 56D.On the drain region 56D, a contact plug 32 is formed that is connectedto a bit line 48. Contact plugs 30 and 31 respectively connected topolysilicon films 52 and 53, which function as capacitor lowerelectrodes, are formed on respective source regions 5S and 6S. Since thehalf pitch cell is constructed, the source regions 5S and 6S formed inthe element forming regions AR that belong to different rows aremutually spaced apart at an interval W2 and aligned along the Ydirection. The drain regions 56D as well as doped channel regions 38, 44formed in the element forming regions AR that belong to different rowsare mutually spaced apart at an interval W1 that is wider than theinterval W2 and aligned along the Y direction.

In each of the element forming regions AR, doped channel regions 5,which correspond to the doped channel regions 5 1 and 5 2 of theforegoing first preferred embodiment, are formed. As in the step shownin FIG. 5, the doped channel regions 5 are formed by implanting p-typeimpurity ions 23 1, 23 2 in the Y direction from diagonally above sothat an implant angle α of the ion implantation controlled within arange tan−1(W2/T)<α≦tan−1(W1/T). Thus, the doped channel regions 5 areformed in the doped channel regions 38 and 44 and in the drain region56D, but are not formed in the source regions 5S and 6S. In the secondpreferred embodiment, for one example, the interval W1 is about 370 nm,the interval W2 is about 110 nm, and the film thickness T is about 120nm.

FIGS. 15 through 19 are cross-sectional views showing, in order ofmanufacturing steps, a method of manufacturing the semiconductor deviceaccording to the second preferred embodiment. First, memory celltransistors shown in FIG. 15 are formed through similar manufacturingsteps to those in the foregoing first preferred embodiment.

FIG. 14 is a top plan view showing a formation pattern of a siliconnitride film 21 when forming the element isolating insulation film 4,corresponding to a portion of FIG. 12. The silicon nitride film 21corresponding to the element forming region AR 11 (denoted by referencecharacter 21 a in FIG. 14) has a first portion 21 1, a second portion 212, and a third portion 21 3, which are connected in that order along theX direction. Likewise, the silicon nitride film 21 that corresponds tothe element forming region AR 21 (denoted by reference character 21 b inFIG. 14) has a fourth portion 21 4, a fifth portion 21 5, and a sixthportion 21 6, which are connected in that order along the X direction.Likewise, the silicon nitride film 21 that corresponds to the elementforming region AR 31 (denoted by reference character 21 c in FIG. 14)has a seventh portion 217, an eighth portion 218, and a ninth portion219, which are connected in that order along the X direction.

The third portion 213, the fourth portion 214, and the ninth portion 219correspond to the source regions 5S and 6S. The second portion 212, thefifth portion 215, and the eighth portion 218 correspond to the dopedchannel regions 38 and 44. The first portion 211, the sixth portion 216,and the seventh portion 217 correspond to the drain region 56D.

The third portion 213, the fourth portion 214, and the ninth portion 219are spaced apart from each other and aligned in that order along the Ydirection. The second portion 212 and the eighth portion 218 are spacedapart from each other and are aligned along the Y direction. The firstportion 211 and the seventh portion 217 are spaced apart from each otherand are aligned along the Y direction. The second portion 212 and thefifth portion 215 are not aligned along the Y direction, and the firstportion 211 and the sixth portion 216 are not aligned along the Ydirection either. The recessed portion 22 has first to ninth sidesurfaces 10A1 to 10A9 that are defined by the silicon substrate 10 belowthe first to ninth portions 211 to 219, respectively.

In a similar manner to the manufacturing step shown in FIG. 5, the dopedchannel regions 5 are formed by implanting p-type impurity ions 231, 232in the Y direction from diagonally above while an implant angle α of theion implantation is controlled within a range tan−1(W2/T)<α≦tan−1(W1/T), with the silicon oxide film 20 and the silicon nitride film 21having been formed. As a result, the doped channel regions 5 are formed,of the second side surface 10A2 and the third side surface 10A3, only inthe second side surface 10A2, of the fourth side surface 10A4 and thefifth side surface 10A5, only in the fifth side surface 10A5, and of theeighth side surface 10A8 and the ninth side surface 10A9, only in theeighth side surface 10A8.

Referring to FIG. 15, after a transistor structure similar to that ofFIG. 2 is obtained, a silicon nitride film is entirely formed by a CVDtechnique. Next, the silicon nitride film is etched back by ananisotropic dry etching technique, thereby forming sidewalls 37 and 43.This provides gate structures 35 and 36 having silicon oxide films 33and 39, conductive films 34 and 40, silicon nitride films 35 and 41,insulating films 36 and 42, and the sidewalls 37 and 43, respectively.

Next, referring to FIG. 16, a silicon oxide film 44 doped with animpurity such as B or P is entirely formed by a coating technique or aCVD technique so as to cover the gate structures 35 and 36.Subsequently, annealing is performed in an O2, N2, or H2 atmosphere.Then, contact holes respectively connected to the source regions 5S, 6Sand the drain region 56D are formed in the silicon oxide film 44 by aphotolithography technique and an anisotropic dry etching technique.Thereafter, contact plugs 30 to 32 respectively connected to the sourceregions 5S, 6S and the drain region 56D are formed by filling up thecontact holes with a polysilicon film doped with an impurity such as P,As, or Sb.

Next, referring to FIG. 17, a silicon oxide film 45 is entirely formedby a CVD technique. Then, a contact hole connected to the contact plug32 is formed in the silicon oxide film 45 by a photolithographytechnique and an anisotropic dry etching technique. Thereafter, a bitline 48 connected to the contact plug 32 is formed by filling up thecontact hole with a barrier metal film 46 of TiN, TaN, WN, TiSi2, COSi2or the like, and a metal film 47 of W, Ti, Cu, Al, or the like.

Subsequently, referring to FIG. 18, a silicon oxide film 49 is entirelyformed by a CVD technique. Then, contact holes respectively connected tothe contact plugs 30 and 31 are formed in the silicon oxide films 45 and49 by a photolithography technique and an anisotropic dry etchingtechnique. Next, contact plugs 50 and 51 respectively connected to thecontact plugs 30 and 31 are formed by filling the contact holes with apolysilicon film doped with an impurity such as P, As, or Sb. Dependingupon the material of which a later-formed capacitor lower electrode isformed, the material of the contact plugs 50 and 51 may be Ti, W, TiN,WN, TaN, or the like.

Then, referring to FIG. 19, a silicon oxide film 56 is entirely formedby a CVD technique. Thereafter, recesses respectively connected tocontact plugs 50 and 51 are formed in the silicon oxide film 56 by aphotolithography technique and an anisotropic dry etching technique.Subsequently, a polysilicon film doped with an impurity such as P, As,or Sb is entirely formed by a CVD technique. Then, the polysilicon filmis polished by a CMP technique until an upper surface of the siliconoxide film 56 is exposed. This forms polysilicon films 52 and 53respectively connected to the contact plugs 50 and 51. The polysiliconfilms 52 and 53 function as capacitor lower electrodes. It should benoted, however, that a metal film of Ti, W, TiN, WN, Pt, Ru, or the likemay be formed in place of the polysilicon films 52 and 53.

Next, the silicon oxide film 56 is removed by an etching technique usingHF. It should be noted, however, that a lower portion of the siliconoxide film 56 may be left unremoved in order to prevent the polysiliconfilms 52 and 53 from collapsing due to mechanical stress during theprocess. Subsequently, an insulating film 54 of SiO2, Si3N4, Ta2O5,Al2O3, HfO, or the like is entirely formed. The insulating film 54functions as a capacitor dielectric film. Then, a conductive film 55 ofpolysilicon, Ti, W, TiN, WN, Pt, Ru, or like is entirely formed. Theconductive film 55 functions as a capacitor upper electrode. With themanufacturing steps described above, a structure shown in FIG. 13 isobtained.

Thus, with the method of manufacturing the semiconductor deviceaccording to the second preferred embodiment, it is possible to suppressreduction in the threshold voltage of memory cell transistors and theoccurrence of the inverse narrow width effect, for the same reasons asthose in the foregoing first preferred embodiment.

Moreover, because the doped channel regions 5 are not formed in thesource regions 5S and 6S, the n-type source regions 5S and 6S do notsuffer from reduction in the impurity concentration arising from theformation of the p-type doped channel regions 5. Therefore, the contactresistance between the respective source regions 5S, 6S and the contactplugs 30, 31 do not increase, and consequently, degradation in datawrite characteristics can be avoided. Furthermore, degradation inrefresh characteristics can be avoided because the electric fieldstrength of the source regions 5S and 6S does not become high.

Third Preferred Embodiment

FIGS. 20 and 21 are cross-sectional views showing, in order ofmanufacturing steps, a method of manufacturing a semiconductor deviceaccording to a third preferred embodiment of the present invention.First, a structure shown in FIG. 8 is obtained through the manufacturingsteps similar to those in the foregoing first preferred embodiment.Next, the silicon oxide film 20 is removed using an aqueous solution ofHF or the like. Then, referring to FIG. 20, the silicon oxide films 151and 152 functioning as the gate insulating film are formed on the uppersurface of the silicon substrate 10 that is in the element formingregions AR1 and AR2. Subsequently, the conductive film 16 is formed onthe silicon oxide films 151 and 152 as well as on the element isolatinginsulation film 4 by a CVD technique or the like. Thereafter, thesilicon nitride film 17 is formed on the conductive film 16 by a CVDtechnique or the like.

Next, referring to FIG. 21, an impurity such as B is ion-implanted intosilicon substrate 10 through the silicon nitride film 17, the conductivefilm 16, and the silicon oxide film 151 and 152. This forms a p-typewell region 11. Then, an impurity such as B, BF2, or In is ion-implantedinto the silicon substrate 10 through the silicon nitride film 17, theconductive film 16, and the silicon oxide films 151 and 152. This formsthe p-type channel cut region 12. Subsequently, an impurity such as B,BF2, or In is ion-implanted into the silicon substrate 10 through thesilicon nitride film 17, the conductive film 16, and the silicon oxidefilms 151 and 152. This forms the p-type doped channel regions 1C and2C. Thereafter, the above-mentioned impurities that have beenion-implanted in the silicon substrate 10 are activated by carrying outa heat treatment.

Next, the silicon nitride film 17 is patterned by a photolithographytechnique and an anisotropic dry etching technique. Subsequently, usingthe silicon nitride film 17 as an etch mask, the conductive film 16 isetched by an anisotropic dry etching technique. Then, an insulating film18 is formed by oxidizing the conductive film 16 with a lamp oxidationtechnique or the like. Thereafter, the n-type source regions 1S and 2Sas well as the n-type drain regions 1D and 2D are formed in the uppersurface of the silicon substrate 10 by ion-implanting an impurity suchas P, As, or Sb using the silicon nitride film 17 as an implant mask.With the manufacturing steps described above, a structure shown in FIG.2 is obtained.

As described above, in the method of manufacturing the semiconductordevice according to the third preferred embodiment, the silicon oxidefilms 151 and 152, which function as the gate insulating films, areformed in the manufacturing step shown in FIG. 20. Thereafter, the dopedchannel regions 1C and 2C are formed in the manufacturing step shown inFIG. 21. Consequently, the impurity contained in the doped channelregions 1C and 2C is not absorbed in the gate insulating films by theheat treatment for forming the gate insulating films. As a result, it ispossible to avoid the reduction in threshold voltage and the occurrenceof the inverse narrow width effect that are caused by reduction in theimpurity concentration in the doped channel regions 1C and 2C.

Accordingly, when forming the doped channel regions 1C and 2C, it isunnecessary to ion-implant a p-type impurity at a higher concentrationthan a desired value; therefore, it is possible to avoid degradations indata write characteristics and refresh characteristics.

It should be noted that in the third preferred embodiment, theabove-described advantageous effects may be obtained even withoutforming the doped channel regions 51 and 52, but it is more effective ifthe doped channel regions 51 and 52 are formed.

Fourth Preferred Embodiment

FIGS. 22 and 23 are cross-sectional views showing, in order ofmanufacturing steps, a method of manufacturing a semiconductor deviceaccording to a fourth preferred embodiment of the present invention.First, a structure shown in FIG. 15 is obtained through themanufacturing steps similar to those in the foregoing second preferredembodiment. Next, referring to FIG. 22, a silicon oxide film 44 isentirely formed by a CVD technique or the like so as to cover the gatestructures 35 and 36. Subsequently, contact holes 60, 62, and 61respectively connected to the source regions 5S and 6S and the drainregion 56D are formed in the silicon oxide film 44 by a photolithographytechnique and an anisotropic dry etching technique.

Next, referring to FIG. 23, a photoresist 63 having such a pattern thatportions thereof that are above the contact holes 60 and 62 are openedis formed by a photolithography technique. Then, using the photoresist63 as an implant mask, an impurity such as P, As, or Sb is ion-implantedat a concentration of about 1E12/cm2 to 1E14/cm2. This forms n-typeimpurity-introduced regions 100 in the respective upper surfaces of thesource regions 5S and 6S. Next, the photoresist 63 is removed. Then,contact plugs 30 to 32 are formed by filling the contact holes 60 to 62with a polysilicon film doped with an impurity such as P, As, or Sb.From this point on, the processes that follow the step shown in FIG. 17are performed, thus completing a semiconductor device.

As described above, with the method of manufacturing the semiconductordevice according to the fourth preferred embodiment, the electric fieldstrength of the source regions 5S and 6S can be further lowered incomparison with the second preferred embodiment by forming theimpurity-introduced regions 100 in the upper surfaces of the sourceregions 5S and 6S. As a consequence, device characteristics such asrefresh characteristics and hot carrier characteristics can be furtherimproved, which accordingly enhances device reliability. Moreover, sincethe impurity-introduced regions 100 are formed only in the sourceregions 5S and 6S, degradation in short channel characteristics of thememory cell transistors can be avoided.

Fifth Preferred Embodiment

FIG. 24 is a top plan view showing a structure of a semiconductor deviceaccording to a fifth preferred embodiment of the present invention. FIG.25 is a cross-sectional view showing a cross-sectional structureconcerning a position along the line XXV-XXV shown in FIG. 24. Referringto FIG. 24, a plurality of element forming regions AR (denoted byreference characters ARa to ARe in FIG. 24) are defined by the elementisolating insulation film 4. The element forming region ARa and theelement forming region ARb, which belong to a common row in a memorycell array, and the element forming region ARd and the element formingregion ARe, which belong to a common row, are each mutually spaced apartand aligned along the X direction. Referring to FIGS. 24 and 25, in eachof the element forming regions AR, impurity-introduced regions 70 and 73are formed in ends of the source regions 5S and 6S with respect to the Xdirection. It should be noted that the doped channel regions 5 may beformed in each of the element forming regions AR, as in the foregoingsecond preferred embodiment.

FIGS. 26 and 27 are cross-sectional views showing, in order ofmanufacturing steps, a method of manufacturing the semiconductor deviceaccording to the fifth preferred embodiment of the present invention.First, referring to FIG. 26, the silicon oxide film 20 and the siliconnitride film 21 are formed in a similar manner to the foregoing firstpreferred embodiment. In addition, a recessed portion 22 a is formed inthe upper surface of the silicon substrate 10 by overetching in theetching for patterning the silicon oxide film 20 and the silicon nitridefilm 21.

Next, referring to FIG. 27, with the silicon oxide film 20 and thesilicon nitride film 21 having been formed, ions 76 and 77 of an n-typeimpurity such as P, As, or Sb are implanted at a concentration of about1E12/cm2 to 1E14/cm2, in the X direction from diagonally above. The ionimplantation is sequentially carried out in opposing directions +X and−X, as indicated by arrows X1 and X2 in FIG. 24.

As for implant angle .beta. of the ion implantation (that is, an angleformed by an implant direction of the impurity ions 76, 77 and adirection of the normal to the upper surface of the silicon substrate10), an implant angle is adopted that satisfies the relationship tan−1(V/U)≦beta≦tan−1 (V/T), where V is the interval between the siliconnitride films 21 adjacent to each other along the X direction, T is thetotal film thickness of the silicon oxide film 20 and the siliconnitride film 21, U is the depth from the upper surface of the siliconnitride film 21 to the bottom surface of the recessed portion 22 a. Forone example, the interval V is about 390 nm, and the depth U is about170 nm.

When the implant angle .beta. is controlled within that range, theimpurity ions 76 and 77 are implanted into portions of the side surfacesof the recessed portion 22 a that are perpendicular to the X direction.For example, of the side surface of the recessed portion 22 a thatcorresponds to the third side surface 10A3 shown in FIG. 14, impurityions 76 and 77 are implanted into a portion perpendicular to the Xdirection. As result, as shown in FIG. 27, n-type impurity-introducedregions 70 and 73 are formed within the upper surface of the siliconsubstrate 10 that is in the element forming regions ARd and ARe,respectively. Meanwhile, because the ion implantation is performed inthe X direction from diagonally above, impurity ions 76 and 77 are notimplanted in portions of the side surfaces of the recessed portion 22 athat are perpendicular to the Y direction.

Thereafter, the recessed portion 22 is formed and the a silicon oxidefilm 13 is formed on the side surfaces and the bottom surface of therecessed portion 22, followed by performing the processes subsequent tothe manufacturing step shown in FIG. 6, as in the second preferredembodiment; thus, a semiconductor device is completed.

As described above, in the method of manufacturing the semiconductordevice according to the fifth preferred embodiment, theimpurity-introduced regions 70 and 73 are respectively formed within theupper surface of the silicon substrate 10 that is in the element formingregions AR. Therefore, even if crystal defects are caused in the siliconsubstrate 10 due to damages arising from, for example, the etching forforming the recessed portion 22, the crystal defects can be covered bythe impurity-introduced regions 70 and 73. As a result, leakage currentresulting from the crystal defects can be suppressed, and refreshcharacteristics can therefore be improved.

Moreover, the impurity-introduced regions 70 and 73 are formed only inportions of the source regions 5S and 6S that are in the vicinity oftheir interfaces with the element isolating insulation film 4, andtherefore, it is possible to avoid degradation in short channelcharacteristics of memory cell transistors.

Sixth Preferred Embodiment

FIGS. 28 through 31 are cross-sectional views showing, in order ofmanufacturing steps, a method of manufacturing a semiconductor deviceaccording to a sixth preferred embodiment of the present invention.FIGS. 28 to 31 show a structure of a memory cell array section in thesilicon substrate 10, in which a memory cell array is formed, and astructure of a peripheral circuit section therein, in which a peripheralcircuit is formed. The following describes an example in which p-channelMOSFETs are formed in the peripheral circuit section.

First, referring to FIG. 28, the silicon oxide film 20, the siliconnitride film 21, the recessed portion 22, and the silicon oxide film 13are formed in the memory cell array section and the peripheral circuitsection in a similar manner to the foregoing first preferred embodiment.In addition, the doped channel regions 51 and 52 are formed in thememory cell array section. Next, a photoresist 80 that covers theperipheral circuit section is formed by a photolithography technique.Then, using the photoresist 80 as an implant mask, ions of an impuritysuch as B or In are implanted into the silicon substrate 10 in adirection perpendicular to the upper surface of the silicon substrate 10through the recessed portion 22 and the silicon oxide film 13. Thisforms a p-type channel cut region 81 in the bottom surface of therecessed portion 22 that is in the memory cell array section.

Next, referring to FIG. 29, after removing the photoresist 80, themanufacturing steps shown in FIGS. 6 through 8 are carried out in asimilar manner to those in the foregoing first preferred embodiment.Specifically, a silicon oxide film 24 having such a film thickness thatit can completely fill up the recessed portion 22 is entirely formed,and subsequently, the silicon oxide film 24 is polished until the uppersurface of the silicon nitride film 21 is exposed; thereafter, thesilicon oxide film 24 is removed to a desired film thickness, and then,the silicon nitride film 21 is removed.

Then, referring to FIG. 30, a photoresist 82 that covers the peripheralcircuit section is formed by a photolithography technique. Thereafter,the p-type doped channel regions 1C and 2C as well as the p-type wellregion 11 are formed within the silicon substrate 10 that is in thememory cell array section by implanting ions of a p-type impurity, usingthe photoresist 82 as an implant mask.

Next, referring to FIG. 31, after removing the photoresist 82, aphotoresist 83 that covers the memory cell array section is formed by aphotolithography technique. Then, n-type doped channel regions 86, ann-type channel cut region 85, and an n-type well region 84 are formed inthe silicon substrate 10 that is in the peripheral circuit section byion-implanting an n-type impurity using the photoresist 83 as an implantmask.

After removing the photoresist 83, the processes subsequent to themanufacturing step shown in FIG. 10 are performed in a similar manner tothe foregoing second preferred embodiment, thus completing asemiconductor device.

As described above, in the method of manufacturing the semiconductordevice according to the sixth preferred embodiment, the channel cutregions 81 are formed only within the bottom surface of the recessedportion 22 in the memory cell array section. In other words, the p-typechannel cut regions 81 are not formed in portions below the n-typesource regions 5S and 6S. For this reason, the electric field strengthof the source regions 5S and 6S is further relaxed in comparison withthe foregoing second preferred embodiment, and therefore, it becomespossible to improve refresh characteristics.

Further, the peripheral circuit section is covered by the photoresist 80when performing the ion implantation for forming the channel cut regions81. Therefore, it is possible to avoid formation of unnecessary channelcut regions 81 within the silicon substrate 10 that is in the peripheralcircuit section.

Seventh Preferred Embodiment

FIGS. 32 through 35 are cross-sectional views showing, in order ofmanufacturing steps, a method of manufacturing a semiconductor deviceaccording to a seventh preferred embodiment of the present invention.First, referring to FIG. 32, the silicon oxide film 20, the siliconnitride film 21, the recessed portion 22, and the silicon oxide film 13are formed in the memory cell array section and the peripheral circuitsection, in a similar manner to the foregoing first preferredembodiment. In addition, the doped channel regions 51 and 52 are formedin the memory cell array section. Next, an impurity such as B or In ision-implanted into the silicon substrate 10 in a direction perpendicularto the upper surface of the silicon substrate 10 through the recessedportion 22 and the silicon oxide film 13. This forms p-type channel cutregions 81 and 90 within the bottom surface of the recessed portion 22that is in the memory cell array section and in the peripheral circuitsection.

Next, referring to FIG. 33, the manufacturing steps shown in FIGS. 6through 8 are carried out in a similar manner to that in the foregoingfirst preferred embodiment. Specifically, a silicon oxide film 24 havingsuch a film thickness that it can completely fill up the recessedportion 22 is entirely formed. Then, the silicon oxide film 24 ispolished until the upper surface of the silicon nitride film 21 isexposed; thereafter the silicon oxide film 24 is removed to a desiredfilm thickness, and then, the silicon nitride film 21 is removed.

Subsequently, referring to FIG. 34, a photoresist 91 that covers theperipheral circuit section is formed by a photolithography technique.Then, the p-type doped channel regions 1C, 2C, and the p-type wellregion 11 are formed within the silicon substrate 10 that is in thememory cell array section, by ion-implanting a p-type impurity using thephotoresist 91 as an implant mask.

Then, referring to FIG. 35, after removing the photoresist 91, aphotoresist 92 that covers the memory cell array section is formed by aphotolithography technique. Next, by ion-implanting an n-type impurityusing the photoresist 92 as an implant mask, an n-type doped channelregion 86, an n-type channel cut region 93, and an n-type well region 84within the silicon substrate 10 that is in the peripheral circuitsection. In the ion implantation for forming the channel cut regions 93,the impurity concentration is set to be about two times the normalconcentration. Thereby, the p-type channel cut regions 90 are cancelledout by the n-type channel cut regions 93.

After removing the photoresist 92, the processes subsequent to themanufacturing steps shown in FIG. 10 are performed in a similar mannerto those in the foregoing second preferred embodiment, thus completing asemiconductor device.

As described above, with the method of manufacturing a semiconductoraccording to the seventh preferred embodiment, the electric fieldstrength of the source regions 5S and 6S can be relaxed for the samereasons as in the foregoing sixth preferred embodiment, and therefore,refresh characteristics can be improved.

In addition, the photoresist 80 shown in FIG. 28 is unnecessary, andconsequently, the number of required photomasks can be reduced incomparison with the foregoing sixth preferred embodiment.

Eighth Preferred Embodiment

FIG. 36 is a top plan view showing a structure of a semiconductor deviceaccording to an eighth preferred embodiment of the present invention.The silicon substrate 10 has a memory cell array section 95 and aperipheral circuit section 96. In FIG. 36, the boundary between thememory cell array section 95 and the peripheral circuit section 96 isdenoted by a hypothetical line 97. In the memory cell array section 95,a plurality of element forming regions AR are defined by the elementisolating insulation film 4, and two memory cells are provided in eachone of the element forming regions AR. In the eighth preferredembodiment, among a plurality of memory cells that constitute the memorycell array, at least a plurality of memory cells that are arranged in anoutermost periphery of the memory cell array are set as dummy cells.Those memory cells that are set as dummy cells do not function as DRAMcells because the contact plugs 30 to 32 are not formed therein.

In the method of manufacturing the semiconductor device according to thesecond preferred embodiment, locations in which the doped channelregions 5 are to be formed are determined by utilizing the shadowingeffect of the silicon nitride film 21 formed on the element formingregions AR adjacent to each other along the Y direction. For thisreason, the shadowing effect of the silicon nitride film 21 cannot beutilized for the element forming regions AR11, AR12, and AR13 that arelocated on ends along the Y direction in the memory cell array section95, and consequently, the doped channel regions 5 cannot be formed atdesired locations. Therefore, it is essential that the memory cellsformed in the element forming regions AR11, AR12, and AR13 be set asdummy cells.

Likewise, in the method of manufacturing the semiconductor deviceaccording to the foregoing fifth preferred embodiment, theimpurity-introduced regions 70 and 73 are formed by the ion implantationin the X direction from diagonally above. For this reason, it may bepossible that, due to the structure of the peripheral circuit section 96or the like, the impurity-introduced regions 70 and 73 are not formedfor the element forming regions AR11, AR31, and AR51 that locate on endswith respect to the X direction in the memory cell array section 95.Therefore, it is inevitable that, of the two memory cells formed in eachof the element forming regions AR11, AR31, and AR51, one that is at theoutermost periphery side be set as a dummy cell.

Thus, in the method of manufacturing the semiconductor device accordingto the eighth preferred embodiment, at least a plurality of memory cellsthat are arranged in the outermost periphery of the memory cell arrayare set as dummy cells. This makes it possible to avoid beforehanddegradation in performance and reliability of a semiconductor devicecaused by the doped channel regions 5 or the impurity-introduced regions70 and 73 being not formed in desired locations.

While the invention has been shown and described in detail, theforegoing description is in all aspects illustrative and notrestrictive. It is therefore understood that numerous othermodifications and variations can be devised without departing from thescope of the invention.

1. A method of manufacturing a semiconductor device having transistorformed on an element forming region defined by a trench isolationregion, comprising: (a) forming a first insulating film on a mainsurface of a semiconductor substrate; (b) forming a conductive film onsaid first insulating film; (c) implanting first impurity ions into saidmain surface through said conductive film and said first insulating filmto form doped channel regions of a first conductivity type; (d)patterning said conductive film to form a gate electrode; and (e)implanting second impurity ions into said main surface that is exposedfrom said gate electrode to form source and drain regions of a secondconductivity type.
 2. The method according to claim 1, furthercomprising: (f) forming a second insulating film on said conductivefilm, said step (f) being performed between said steps (b) and (c); (g)patterning said second insulating film, said step (g) being performedbetween said steps (c) and (d), wherein: in said step (c), said firstimpurity ions are implanted into said main surface through said secondinsulating film, said conductive film and said first insulating film,and in said step (d), said conductive film is patterned by an etchtechnique using said second insulating film patterned in said step (g)as an etch mask.
 3. The method according to claim 1, wherein: in saidstep (a), said first insulating film is formed using a lump oxidationapparatus at about 900 to 1100° C.
 4. The method according to claim 1,further comprising: (h) forming a trench in said main surface; (i)forming a thermal oxidation film on side surfaces and a bottom surfaceof said trench by a thermal oxidation technique at about 900 to 1150°C., using a single wafer-type lamp oxidation apparatus; and (j) forminga third insulation film to fill said trench; wherein said steps (h), (i)and (j) are performed before said step (a) to form said trench isolationregion.
 5. The method according to claim 1, wherein said step (c)further includes: (c-1) implanting third impurity ions into said mainsurface deeper than a bottom of said trench isolation region throughsaid conductive film and said first insulating film to form channel wellregions of said first conductivity type; (c-2) implanting fourthimpurity ions into said main surface so as to contact said bottom ofsaid trench isolation region through said conductive film and said firstinsulating film to form channel cut regions of said first conductivitytype.
 6. The method according to claim 5, wherein in said step (c) saidfirst, second and third impurity ions are implanted substantially in asame region in plane view.
 7. The method according to claim 1, furthercomprising: (k) forming an interlayer insulation film after said step(e); (l) forming a contact hole connected to said source and drainregions in said interlayer insulation film; (m) forming a conductiveplug in said contact hole; (n) forming a lower electrode of a capacitorover said conductive plug, (o) forming a dielectric film on said lowerelectrode; and (p) forming an upper electrode of said capacitor on saiddielectric film.